The present invention relates to a semiconductor device having electrically erasable and rewritable nonvolatile memory transistors; and, more specifically, the invention relates to a technique that is applicable to a semiconductor device having nonvolatile memories, which uses flip-flops (nonvolatile memory circuits) including plural nonvolatile memory transistors as a storage unit.
A flash EEPROM memory has been provided as a nonvolatile memory, which is capable of electrically erasing data as well as electrically writing data collectively in a specific unit, which memory is hereunder referred to as a flash memory. The flash memory has memory cells configured with electrically erasable and writable nonvolatile memory transistors, which memory is capable of erasing data and programs that are written temporarily in memory cells and rewriting new data and programs in the memory cells.
Therefore, after integrating the flash memory or a microcomputer containing the flash memory into an application system, when modifications of data, corrections of bugs in a program, and updates of the program, and the like become necessary, the data and programs stored in the flash memory can be modified on the application system, which accordingly achieves a reduction of the development term of the application system and gives flexibility to the program development of the application system.
Recently, on the other hand, a system semiconductor device has been provided, in which a central processing unit (Hereunder, also referred to as a CPU) operating as a data control device, a DRAM (Dynamic Random Access Memory) serving as a large scale memory, an SRAM (Static Random Access Memory) serving as a high speed memory or a cache memory, and other functional circuits are integrally formed on one semiconductor substrate (hereunder, also referred to as a system LSI), whereby one semiconductor device can form one complete system. This type of system LSI contributes to a size reduction of a PCB and a packaging substrate, and exhibits a significant effect in miniaturization and weight reduction of portable equipment, such as portable telephones, portable data terminals, and the like.
The inventors of the present invention have examined the prior art from the following aspect A and aspect B.
The aspect A involves provision of nonvolatile memory transistors with single layer polysilicon gates, and the aspect B involves the use of flip-flops, including the nonvolatile memory transistors, as a storage unit.
As a result, the inventors have discovered, with regard to aspect A, the U.S. Pat. No. 5,440,159, the U.S. Pat. No. 5, 504, 706, Japanese Unexamined Patent Publication No. Hei 4 (1992)-212471 (corresponding to U.S. Pat. No. 5,457,335), and a thesis by Osaki et al. on xe2x80x9cA single poly EEPROM Cell Structure for use in Standard CMOS Processesxe2x80x9d published in the IEEE Journal of Solid-state Circuits, VOL. 29, No.3, March 1994, pp311-316.
On the other hand, the inventors discovered, with regard to aspect B, Japanese Unexamined Patent Publication No. Hei 5(1993)-314789, Japanese Unexamined Patent Publication No. Hei 6(1994)-76582, and Japanese Unexamined Patent Publication No. Hei 10(1998)-334691 (corresponding to U.S. Pat. No. 5,912,841). The Japanese Unexamined Patent Publication No. Hei 5(1993)-314789 discloses a technique in which two electrically rewritable nonvolatile memory (EPROM) transistors are constructed by using flip-flops composed of a drive transistor and two load transistors as a storage unit, and in which redundant addresses of a relief circuit are stored.
The inventors"" examination of the foregoing documents revealed the following points. First of all, the first problem discovered by the inventors was that, in the flip-flop circuit composed of the drive transistor (nonvolatile memory transistor) and the two load transistors, as disclosed in the Japanese Unexamined Patent Publication No. Hei 5(1993)-314789, the initial threshold voltage in which the floating gates do not hold any charges at all, the threshold voltage in the writing/erasing state, and the word line potential in reading greatly influence the rate of occurrence of readout errors resulting from a deterioration of the charge holding characteristics.
FIG. 25 shows a flip-flop circuit including the nonvolatile memory transistor that the inventors examined, illustrating a state in which writing is executed to one nonvolatile memory transistor 223, and, thereafter, the reading is executed by applying the supply voltage Vcc to the supply line. In FIG. 25, reference numerals 220 and 221 denote a p-channel load transistor; and reference numerals 222 and 223 denote an n-channel nonvolatile memory transistor. Since the one transistor 222 of the two nonvolatile memory transistors has the initial threshold voltage (VthL) and the other transistor 223 has the high threshold voltage (VthH), while the potential of the power supply line rises from 0 Volt to the power supply voltage Vcc, the latch is locked; and, accordingly, Vcc (H level) is applied to the drain of the nonvolatile memory transistor 223 having the high threshold voltage (VthH) and to the gate of the nonvolatile memory transistor 222 having the initial threshold voltage (VthL) acting as the so-called disturbing voltage. In this state of disturbance, a stress acts in a direction such that the charges stored in the floating gate of the nonvolatile memory transistor 223 having the high threshold voltage (VthH) are pulled out toward the drain terminal; on the other hand, a stress acts in the direction such that the charges are poured into the floating gate of the nonvolatile memory transistor 222 having the initial threshold voltage (VthL). Since the semiconductor device is designed on the premise that it operates continuously for ten years, it has to be considered that the stresses which act on the nonvolatile memory transistors 222, 223 are applied continuously for ten years. Therefore, the rise of the threshold voltage in the nonvolatile memory transistor 222 having the initial threshold voltage (VthL), namely the charge gain, and the fall of the threshold voltage in the nonvolatile memory transistor 223 having the high threshold voltage (VthH), namely the charge loss, occur at the same time. In case a gate oxide film is made thin, the threshold voltages of the two nonvolatile memory transistors 222, 223 approach an equal value comparably easily, and it is believed that a readout error occurs due to a conversion of latched data. Thus, the inventors discovered that the flip-flop circuit with the supply voltage Vcc always applied as shown in FIG. 25 is not resistant to the disturbing voltage.
The second problem discovered by the inventors is that, in the vertically stacked-structure comprising memory cells of the floating gates and the control gates, namely the stacked gate memory cells, the complicated memory cell structure increases the manufacturing cost. Especially, in the so-called system LSI product that incorporates the flash memory, which has experienced rapid growth in the market in recent years, together with high-speed logic circuits, a DRAM, and the like, the application of the stacked memory cells to the flash memory leads to an increase in the manufacturing cost. The investigation by the inventors finds that this is caused by an increase in the number of photo masks and the manufacturing processes. That is, the tunnel oxide film of a flash memory is thicker than the gate oxide film of a logic circuit transistor or the gate oxide film of a DRAM cell transistor. This requires a mask for separately manufacturing a tunnel oxide film, a mask for adding a polysilicon film for the floating gate of the flash memory, a mask for processing word lines of the flash memory, an impurity injection mask for forming a drain region of the flash memory, and the impurity injection mask for forming a low density N-type source/drain region and a low density P-type source/drain region for high withstand voltage transistors constituting a write/erase circuit; therefore, the number of masks to be added amounts to six at the lowest. Accordingly, it becomes difficult to provide a low-priced system LSI that incorporates a flash memory using stacked gate memory cells in terms of the cost. In order to solve this problem it is necessary to form the nonvolatile memory transistors with a single layer polysilicon gate structure.
However, in regard to the gate oxide film thickness of the nonvolatile memory transistors which have a layer polysilicon gate structure, it is advisable to examine the relation with the gate oxide film thickness of the MIS transistors in the other circuits, which are incorporated together with the nonvolatile memory transistors. The inventors"" examination indicates that the limit of the rewrite frequency in the nonvolatile memory transistor has a correlation with the gate oxide film thickness, and the gate oxide film thickness should be made thick to delay the deterioration of the data holding performance. However, in order to not complicate the manufacturing processes of the semiconductor integrated circuit, it is advisable to form the gate oxide film of the nonvolatile memory transistors having the single layer gate structure and the gate oxide film of the MIS transistors in the other circuits so that they have the same thickness.
The inventors further examined the aspects of using a plurality of the nonvolatile memory transistors single layer polysilicon gate structure in series connection, halting the application of the voltage to the nonvolatile memory transistors directly after reading the nonvolatile memory transistors which have the single layer polysilicon gate structure, holding data read out from the nonvolatile memory transistors by a volatile data latch circuit, and processing the data held by the data latch circuit by an error-correcting code (ECC) circuit, etc. In regard to these proposals, there was not any disclosure in the documents found in the above investigation of the prior art.
An object of the present invention is to enhance the data holding performance of the nonvolatile memory transistors connected in a static latch configuration over a long period of time.
Another object of the invention is to simplify the device structure of the nonvolatile memory transistors connected in the static latch configuration.
Another object of the invention is to provide a semiconductor device incorporating a nonvolatile memory that remarkably lowers the rate of occurrence of readout errors, without adding an entirely new process to the normal logic circuit process or the general purpose DRAM process.
Another object of the invention is to provide a technique that uses the nonvolatile memory transistors configured with single layer polysilicon gates for the relief circuit of a memory module or a memory circuit.
The foregoing and other objects and novel features of the invention will become apparent from the following descriptions and the accompanying drawings.
Typical aspects and features of the invention disclosed in this application will be outlined briefly as follows.
[1] The first aspect of the invention is to read out information stored in the nonvolatile memory transistors connected in static latch configuration, such as a flip-flop (self-latch), thereafter immediately stop application of the operating voltage to the nonvolatile memory transistors, and shorten the period of the voltage applied, so as to enhance the information holding performance over a long term.
That is, the nonvolatile memory formed on a semiconductor substrate includes plural nonvolatile memory circuits that include a pair of series circuits of load elements and nonvolatile memory transistors, which are connected in a static latch configuration; a program control circuit that writes information into the nonvolatile memory circuits; a volatile latch circuit that operates to latch information read from the nonvolatile memory circuits; and a readout control circuit that controls the volatile latch circuit to latch the information read from the nonvolatile memory circuits.
As long as the operating supply voltage is inputted, the volatile latch circuit holds the information read from the nonvolatile memory circuits. In this state, the nonvolatile memory circuits are not needed to maintain the static latch operation. Thereafter, it is beneficial to stop the supply of the operating voltage for the static latch operation by the nonvolatile memory transistors.
Preferably, the readout control circuit adopts an automatic power-off function. For example, the readout control circuit supplies the operating supply voltage for the static latch operation to the nonvolatile memory circuits in response to the instruction for a reading operation, and stops the supply of the operating supply voltage, after the volatile latch circuit completes the latch operation in response to the static latch operation.
This makes it possible to avoid a useless voltage application to the nonvolatile memory transistors, which shortens the period during which the nonvolatile memory transistors are exposed uselessly to the voltages that create the charge gain and the charge loss, thereby enhancing the information holding performance over a log term.
The nonvolatile memory circuit is used for the storage of relief information for relieving defective circuit portions. It is advisable to give the instruction of the reading operation in response to the reset instruction to the semiconductor device, when there presumably exists information that has to already be reflected to the functions of the internal circuits, in a stare that the semiconductor device is operable as with the relief information.
And, assuming that there exists information that is indispensable for the normal operation of the semiconductor device, such as the relief information, it is recommendable to add an ECC circuit that accepts the information latched by the volatile latch circuit and implements error corrections, in order to further enhance the long-term reliability of the information stored in the nonvolatile memory circuit.
[2] The basic circuit configuration for the self-latch operation preferably adopts a pair of nonvolatile memory transistors as the drive transistor. That is, the nonvolatile memory circuit operating as the self-latch is configured with a first conductive type transistor having a source, drain, and gate as the load, and a second conductive type nonvolatile memory transistor having a source, drain, floating gate, and control gate. The series circuit of the load and the nonvolatile memory transistor have an output node to couple the load transistor with the nonvolatile memory transistor and a control node to couple the gate of the load transistor witb the control gate of the nonvolatile memory transistor. The output node of one series circuit is mutually connected to the control node of the other series circuit to form the static latch configuration, and complementary data lines are connected to the output nodes of both of the series circuits.
The programming of a pair of nonvolatile memory transistors in the nonvolatile memory circuit is arranged, for example, to supply complementary voltages to the complementary data lines and inject hot electrons into the floating gate of one nonvolatile memory transistor. In the reading operation of the nonvolatile memory circuit, the static latch operation in accordance with the threshold voltage difference of a pair of the nonvolatile memory transistors by supplying the operating supply voltage to a pair of the series circuit with a specific speed acquires complementary signals on the complementary data lines.
[3] The self-latch preferably adopts a series connection configuration of the nonvolatile memory transistors, in order to enhance or improve the information holding performance. That is, the nonvolatile memory circuit is configured with the first conductive type transistor equipped with a source, drain, and gate as the load, and the second conductive type nonvolatile memory transistor equipped with a source, drain, floating gate, and control gate. The series circuit of the load transistor and the non-volatile memory transistor possesses an output node to couple the load transistor with the nonvolatile memory transistor, a program node to connect another nonvolatile memory transistor in series to the nonvolatile memory transistor coupled with the output node, and a control node to commonly couple the gate of the load transistor and the control gate of the nonvolatile memory transistor. A pair of the series circuits has a static latch configuration in which the output node of one series circuit is mutually connected to the control node of the other series circuit, complementary data lines are connected to the output nodes of both of the series circuits, and complementary program control lines are connected to the program nodes of both of the series circuits.
The programming of a pair of the nonvolatile memory transistors in the nonvolatile memory circuit is arranged, for example, to supply complementary voltages to the complementary program control lines and inject hot electrons into the floating gates of both the nonvolatile memory transistors of one series circuit. In the reading operation of the nonvolatile memory circuit, the static latch operation in accordance with the threshold voltage difference of the nonvolatile memory transistors between a pair of the series circuits by supplying the operating supply voltage to a pair the series circuit with a specific speed acquires complementary signals on the complementary data lines. In case of the nonvolatile memory transistors each having gate insulating films of equal thickness, the probability that the floating gate emits hot electrons by the charge loss to thereby invert the threshold voltage state decreases with two transistors in series, compared with one. Therefore, the series configuration of plural nonvolatile memory transistors makes it possible to enhance or improve an insufficient information holding performance in terms of the gate insulating film thickness of the nonvolatile memory transistors.
[4] The second aspect of the invention lies in the single layer polysilicon gate structure of the nonvolatile memory transistor. That is, the nonvolatile memory transistor preferably includes a MIS transistor having the second conductive type source and drain formed in the first conductive type semiconductor region, a gate insulating film formed on a channel between the source and the drain, and a floating gate formed on the gate insulating film, and a control gate formed in the second conductive type semiconductor region, underlying a gate insulating film formed beneath an extended portion of the floating gate.
The thickness of the gate insulating film of the nonvolatile memory transistor is preferably determined in consideration of the necessary withstand voltage and the relation of the gate insulating film thickness with the other circuits. For example, it is recommendable to employ a high voltage operational MIS transistor having a comparably thick gate insulating film for the MIS transistors contained in the nonvolatile memory circuit and the program control circuit (the term MIS transistor used in this specification is a generic name for the insulated-gate field-effect transistor), and to employ a low voltage operational MIS transistor having a comparably thin gate insulating film to the MIS transistors contained in the volatile latch circuit and the readout control circuit.
When a logic circuit and an external interface circuit each having the MIS transistors are included on the semiconductor substrate, the external interface circuit employs a comparably thick gate insulating film for increasing the static withstand of the input MIS transistors connected to the external terminal. On the other hand, in the semiconductor integrated circuit that steps down the operating supply voltage, such as 3.3 volts supplied from outside, and uses the stepped down voltage as the operating voltage for the internal circuit, such as the logic circuit, the MIS transistors for the external interface circuit that operate by receiving 3.3 volts have a thick gate insulating film, compared to those of the MIS transistors for the internal circuit. In consideration of this point, it is advisable to set the gate insulating film thickness of the nonvolatile memory transistors and that of the MIS transistors contained in the external interface circuit into a substantially equal thickness (within the allowance due to the process dispersion). In other words, the gate insulating film of the MIS transistors for the nonvolatile memory transistors and the gate insulating film of the MIS transistors contained in the external interface circuit are only needed to be manufactured at the same time, with one and the same process or with a common photo-mask.
Thus, the arrangement to make the gate insulating film thickness of the nonvolatile memory transistors having the single layer gate structure and the gate insulating film thickness of the MIS transistors in the other circuits into one uniform thickness achieves a long-term information holding performance for the nonvolatile memory circuit, while not complicating the manufacturing process of the semiconductor device.
In view of the manufacturing process capable of forming the nonvolatile memory elements, such as the single layer polysilicon process, the floating gates of the MIS Transistors constituting the nonvolatile memory transistor, the gates of the MIS transistors contained in the logic circuit, the gates of the MIS transistors contained in the external interface circuit, and the gates of the MIS transistors contained in the DRAM are preferably formed with an equal thickness within the allowance due to the process dispersion. That is, an employment of the single gate process, such as the single polysilicon process, will provide a semiconductor integrated circuit that incorporates a nonvolatile memory that has an excellent data holding performance together with DRAM and so forth, such as a system LSI.
[5] The third aspect is a memory circuit for relief information as a use of the nonvolatile memory. Here, the semiconductor device includes a to-be-relieved circuit and a relief circuit that replaces the to-be-relieved circuit on the substrate, and the nonvolatile memory circuit is used as a memory circuit for holding relief information that specifies the to-be-relieved circuit to be replaced by the relief circuit.
The semiconductor device may be provided with a fuse programming circuit that stores the relief information in accordance with a fusing state of a fuse element, as another circuit to store the relief information for the relief circuit. The combined use of the fuse programming circuit for the relief of defects detected on the wafer stage and the programming circuit for the relief of the defects detected after the burn-in makes it possible to improve the relief efficiency, in other words, to enhance the yield of the semiconductor device. The use of the fuse programming circuit only cannot relieve the defects after the burn-in. The use of the electrical programming circuit only will enlarge the circuit scale or the chip area.
The to-be-relieved circuit may be a memory cell array with a DRAM built in. Or, the to-be-relieved circuit may be a memory cell array of a microcomputer built-in DRAM. Or, the to-be-relieved circuit may be a memory cell array of a microcomputer built-in SRAM.
[6] In order to ultimately reduce the readout defect rate, the semiconductor device may be configured so as to make a part of the plural nonvolatile memory circuits hold error correction codes in relation to the relief information held by the remaining nonvolatile memory circuits, and to provide an ECC circuit capable of error corrections in relation to the readout information of the plural nonvolatile memory circuits.
The guarantee of the error correction function by the ECC circuit may be achieved by providing the program control circuit with a write-in inhibit mode to the nonvolatile memory circuit.